Hy-Ad001 User Manual

. Integrator/IM-AD1 User Information Copyright © 2001-2003. All privileges reserved. Supply Drunk driving 0163B. Integrator/IM-AD1 User Information Copyright © 2001-2003. All privileges reserved. Discharge Information Date March 2001 November 2003 Proprietary Notice Words and logos noted with as normally mentioned below in this proprietary notice.

Other brands and names mentioned thus may be the trademarks of their particular owners. Conformance Notices This section consists of conformance updates.

Federal Communications Commission See This device is check devices and consequently will be exempt from part 15 of the FCC Guidelines under section 15.103 (d). CE Statement of Conformity The system should be run down when not in use. The Integrator generates, utilizes, and can radiate radio frequency energy and may trigger harmful disturbance to radio stations communications. Copyright © 2001-2003. All rights reserved.

Supply Drunk driving 0163B. Hardware Reference Left arm Driving under the influence 0163B About this publication. Viii Suggestions.

Xi About thé Integrator/lM-AD1. 1-2 Interface module functions and architecture. 1-4 Hyperlinks and LEDs. 1-6 Care of segments. 1-7 Fitting the interface component. 2-2 Setting up the logic module.

Material Part 4 Benchmark Design Instance 4.10 4.11 4.12 4.13 Appendix A Sign Descriptions Appendix M Mechanical Specification Glossary CAN user interface. 3-14 ADC and DAC interfaces. 3-18 About the style example. 4-2 Instance APB register peripheral. Preface This preface presents the Integrator/IM-AD1 interface component and its consumer documentation. It consists of the subsequent sections:.

About this guide on web page viii. Feedback on page xi.

Left arm Driving under the influence 0163B Copyright © 2001-2003. All rights arranged. Preface About this guide This publication provides user info for the Hand Integrator/IM-AD1 user interface component.

It explains the major functions and how to make use of the user interface component with an Integrator development platform. Designed viewers This publication is created for all programmers who are usually making use of an Integrator/LM reasoning component to develop ARM-based devices. Typographical conventions The following typographical conventions are utilized in this guide: italic vivid monospace monospace monospacé italic monospace strong Further reading This area lists journals from both Supply Limited and third parties that provide additional info on building code for the Limb household of processors. Hand periodically provides up-dates and corrections to its documents. The adhering to publication offers info about Multi-lCE:. Multi-ICE Usér Tutorial (Arm rest DUI 0048). Third-party paperwork The following documents provide info about third-party parts used on the lntegrator/lM-AD1:.

CC770 Take a position Alone CAN Controller Target Standards Robert Bosch GmbH. Opinions ARM Limited welcomes feed-back on both thé Integrator/lM-AD1 ánd its documents. Feedback on this document If you have got any responses on this publication, please send e-mail to.

the document name. the document amount. the page number(t) to which your responses utilize.

Preface Copyright © 2001-2003. All privileges reserved.

Supply Drunk driving 0163B. Part 1 Introduction This section presents the Integrator/lM-AD1. It consists of the following sections:. About thé Integrator/lM-AD1 on web page 1-2.

Interface module features and architecture on page 1-4. Hyperlinks and LEDs on web page 1-6. Treatment of quests on page 1-7.

The user interface module is made to end up being installed on top of the reasoning component and offers connection for peripherals in the reasoning module FPGA. Physique 1-1 on page 1-3 displays the design of the lM-AD1 and recognizes the fittings. The IM-AD1 can end up being utilized to carry out extra peripherals to help software development, for instance additional timers or á vector interrupt controller. (L7) Left arm Drunk driving 0163B Copyright © 2001-2003. All privileges reserved. Launch Stepper engine control (M19 and J20) SPI2 (L13) SPI1 (L11) Chemical/A Results (M2) GPIO A (L17) GPIO M (L16) A/N Advices (J1) (M3A and J3B)) Physique 1-1 Integrator/IM-AD1 design.

Introduction Interface module functions and architecture This area represents the main features of the interface module and its architecture. 1.2.1 Features The primary features of the interface module are usually as follows:.

twó Bosch CC770 Control Area Network (May) controllers. Part 3 Hardware Reference. Supply Driving under the influence 0163B Stepper engine interfaces May interfaces D to A converter A new to Deb converter PWMs UART interface Physique 1-2 Integrator/IM-AD1 block diagram Copyright © 2001-2003. All privileges reserved. Launch Links and LEDs The interface module offers one link and one LED.

These are the CONFIG hyperlink and CONFIG LED. Fitting the CONFIG hyperlink locations all of the modules in the bunch on which the user interface module will be mounted into CONFIG mode. This mode enables you to réprogram the FPGA image in the settings display on the reasoning module(h) making use of Multi-ICE (find the user guidebook for the reasoning module). Care of segments This area contains assistance about how to prevent harm to your Integrator quests. To avoid harm to your Integrator system, see the adhering to precautions:.

When getting rid of a primary or reasoning module from a mothérboard, or when isolating modules, take care not really to harm the connectors. Launch Copyright © 2001-2003. All privileges reserved. Hand DUI 0163B.

Part 2 Obtaining Started This section details how to set up and start using the reasoning module. It contains the following sections:.

Fitted the interface module on page 2-2. Setting up the reasoning component on page 2-3. Working the check software on page 2-4 Left arm Drunk driving 0163B Copyright ©. Obtaining Started Appropriate the user interface module The user interface module is definitely installed at the top of a bunch of up to four logic modules. Nevertheless, it only provides user interface contacts for the logic module instantly beneath it. Number 2-1 displays an example system including a primary component and logic module connected to an Integrator/AP (observe the Integrator/AP User Manual for even more details).

Change 3 Open Switch 4 Open. The logic component will today be set up with the illustration design. If the IM-AD1 can be not currently fitted, install it on top of the reasoning component and the system is prepared to use. ARM Drunk driving 0163B Installdirectory IM-AD1 configure plan file. Obtaining Started Operating the check software program The provided test plan checks each of thé interfaces on thé IM-AD1. Thé instance logic component configuration must end up being programmed into the logic module before the test system can end up being operate. The test software demands various cables to become linked to the IM-AD1, information of.

Section 3 Hardware Reference This section explains the hardware interfaces and controIlers on the user interface module. This chapter includes the following sections:. Distinctions in sign routing between backed logic quests on web page 3-2. UART interface on web page 3-3. Equipment Reference Distinctions in signal routing between backed logic segments The lntegrator/LM-XCV600E+ and LM-EP20K600E+ logic module forms path the indicators from the interface module in different ways as follows:. LM-XCV600E+ is usually fitted with a XiIinx FPGA and tracks the user interface module ABANK59:0 signals to bank 0 on the FPGA and the BBANK53:0 signals to loan provider 1 on the FPGA. UART user interface The interface module offers one serial transcéiver suitable for make use of with the PrimeCell UART (PL011) or various other related peripheral.

Figure 3-1 shows the architecture of the UART interface. The signals associated with the UART user interface are assigned to the EXPIM socket pins as shown in Table 3-1. Hardware Guide The serial user interface uses a 9-flag D-type man connector for which the pin number numbering can be demonstrated in Body 3-2. Table 3-2 displays the signal project for the connection. The serial interfaces signals run at RS232 indication ranges. Serial port functionality corresponds to the DTE configuration. Table 3-2 Serial connection signal assignment SERDCD SERRXD.

This user interface module provides two fittings for SPI ports. They are connected straight to the reasoning component FPGA and are used by thé SSP PrimeCeIl (PL022) in the illustration configuration. Table 3-3 shows the task of the SPI indicators to the logic module signals on the EXPIM connection. Hardware Referrals PWM user interface The user interface module is certainly installed with a dual MOSFET change. This provides two outputs that can end up being set up as Heartbeat Thickness Modulated (PWM) outputs or used as DC buttons to change external a lot. The MOSFET can switch a good deal at up to 30V.

Although the MOSFET is usually ranked for 3A, because of the power dissipation of the package the optimum load current is usually 2.5A if just one PWM output is utilized or 1.75A if both results are used. Desk 3-5 shows the signal assignment. Left arm DUI 0163B PWM1+Sixth is v PWM2+V PWM1SWITCH PWM2Change PWM1FB PWM2FB PWMGND PWMGND Copyright © 2001-2003. All privileges reserved. Hardware Reference Table 3-5 PWM connection signals Description PWM offer voltage PWM turned load connection PWM feedback transmission PWM ground. Hardware Guide Stepper motor interface The IM-AD1 offers four stepper engine interfaces.

Two of these, Action 1 and Action 2, are supplied with on-board motor drivers for bipolar motors. The remaining two, Action 3 and Phase 4, provide logic-level indicators that are linked to two 10-pin headers. This allows you to link to off-board engine motorists.

The present limit is certainly set by the reference point voltage and feeling resistor according to the equation: maximum Consequently, with a 0.1Ω sense resistor fitted: = 0.15 x 10 = 1.5A peak The reference voltage, and therefore the present control, can end up being altered by altering the beliefs of the divider resistors. Hardware Reference Sign Phase2PH1 STEP2PH2 STEP2PH3 Stage2PH4 Action3ENA Phase3ENB STEP3PH1 Phase3PH2 Stage3PH3 Action3PH4 Action4ENA Stage4ENB STEP4PH1 Stage4PH2 STEP4PH3 Action4PH4 3.5.3 Stepper engine connectors Physique 3-6 shows the flag numbering of the stepper electric motor connectors. 3-10 Desk 3-6 Stepper electric motor interface signals (continuing) EXPB Description connector.

Desk 3-7 shows the sign assignment. Hand Drunk driving 0163B STEP1VSS STEP2VSS Phase1O1 Action2O1 STEP1O2 Stage2O2 Action1O3 STEP2O3 Phase1O4 Stage2O4 STEPGND STEPGND Copyright © 2001-2003. All rights reserved. Hardware Reference Desk 3-7 Stepper engine connector indicators Description Stepper electric motor source Stepper engine drive output 1 Stepper electric motor drive result 2 Stepper motor drive output 3 Stepper motor drive output 4. Equipment Reference GPIO The user interface module provides two fittings for GPIO interfaces.

Each connection provides 32 GPIO ranges connected directly to the reasoning module FPGA. The fittings are shown in Body 3-7. 3-12 +3V3 GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 GPIOA8. Equipment Research The illustration configuration contains two simple 32-bit GPIO controllers. GPIOA31:0 link to the EXPIM indicators IMABANK31:0 and GPIOB31:0 connects to the EXPA indicators B31:0. The B31:0 signals can end up being supervised on the reasoning analyzer connector L7.

Left arm Drunk driving 0163B Copyright ©. Hardware Reference CAN interface The IM-AD1 has two CAN interfaces offered by Bósch CC770 serial communications controllers. The system interfaces are usually supplied by PhiIips TJA1050 transceivers, each able of 1Mt/s data transfer.

Figure 3-8 shows the structures of the CAN user interface. The CAN controllers are 5V products and are usually supported by buffers at their interface with the 3.3V program busses. All user interface signals are routed to the logic module. The CAN controllers are usually supported by an AHB user interface instantiated into the reasoning module program code example supplied with the lM-AD1.

The tránsmit and receive data signals, CANxTXD ánd CANxRXD, at thé EXPIM connectors are not really used for the normal procedure of the interfaces. Hardware Research You connect the CAN interfaces through the 9-pin D-type attaches M3A (best) and L3B (bottom level), with CAN1 linking to M3A. Physique 3-9 displays the flag places for this kind of connector. 3-16 Desk 3-8 May interface signal task (continued) EXPIM Transmission connector. Table 3-9 shows the sign assignment. ARM Driving under the influence 0163B Desk 3-9 CAN connector sign assignments Copyright © 2001-2003.

All privileges reserved. Hardware Reference Not connected Not connected May1L CAN2L Not connected Not connected May1H May2H Not really connected Not connected Not really connected Not really connected 3-17. DACnWR All of the interface signals are routed to thé FPGA on thé logic module. The ADCs and DAC are backed by an AHB interface that is usually instantiated in the reasoning module code example supplied with the lM-AD1.

3-18 ADD15:05V. Table 3-10 shows the project of thé ADC ánd DAC user interface indicators to the logic module indicators on the EXPIM connection.

Signal ADD15:0 ADT/R ADnOE ADC1nC0NV ADC1nCS ADC1nWR ADC1nRD ADC2nC0NV ADC2nCS ADC2nWR ADC2nRD ADC1BUSY ADC2BUSY DACnCLR DACnLDAC DACA0 DACnCS DACnWR ADCCLK Thé ADCs are clocked from a 4MHz oscillator. Hardware Reference point The anaIog inputs to thé ADCs are usually buffered by LMV324 operational amplifiers (op-ámps). The op-ámps are set up to give unity gain but the inputs possess a resistive divider panel that divides the insight voltage by 2. A 0-5V input signal range at the buffer inputs offers a 0-2.5V complete range at the ADC input.

Physique 3-12 displays the pinout óf the DAC user interface connection (L2). ARM DUI 0163B Copyright © 2001-2003. All privileges reserved. Hardware Benchmark VOUTA VOUTB Shape 3-12 DAC connector pinout 3-21. Hardware Referrals 3-22 Copyright © 2001-2003.

All privileges reserved. Left arm Drunk driving 0163B. Section 4 Research Design Illustration This section identifies how to set up and begin using the supplied example style. It consists of the following sections:. About the design instance on page 4-2. Example APB sign up peripheral on page 4-8.

Research Design Example About the style instance This part details the reference point design example supplied with the user interface module. The user interface module is usually not fitted with any programmable devices because it is definitely intended to provide interfaces for peripheraIs instantiated into á reasoning component FPGA. The user interface module style example for the logic module is provided in VHDL.

Program Table 4-1 offers a overview explanation of the provided VHDL documents. A more detailed explanation of each VHDL wedge is included within the data files in the type of comments. File Explanation This file can be the top-Ievel VHDL that instantiatés all of thé interface for the instance. The VHDL fór IMAD1fpga thé PrimeCell interfaces are usually not supplied but are usually accessible from Hand as individual products. Reference point Design Example File Explanation This will be the AHB multiplexor that attaches the read information buses and thé HRESP ánd HREADY AHBMux7S1M indicators from all óf the slaves tó the AHB expert.

Hp Envy 7640 User Manual

AHBZBTRAM An SSRAM controller stop to support word, halfword, and byte functions to thé SSRAM on thé reasoning component. 0xN0000000 0xE0000000 0xChemical0000000 0xG0000000 The Integrator program implements a dispersed address decoding structure in which each primary or logic module is certainly responsible for solving its personal address area. It can be important when implementing a reasoning module design, to assure that the component responds to all storage accesses in the appropriate memory area (see the user manual for your motherboard). Guidebook for more info). 4.1.5 Integrator/IM-AD1 memory chart The storage model for the style is shown in Table 4-2 and assumes that the reasoning module is usually installed in place 0.

User Manual Example

Table 4-3 Integrator/IM-AD1 storage map Gadget logic module APB signs up UART0 SPICS. Limb Driving under the influence 0163B Desk 4-3 Integrator/IM-AD1 memory map (carried on) Gadget STEPPERB GPIOA GPI0B Réserved SSRAM ADC/DAC Cópyright © 2001-2003.

All rights reserved. Benchmark Design Instance Tackle 0xChemical0C00000 0xChemical0D00000 0xChemical0E00000 0xC1000000 0xChemical2000000 0xChemical3000000 0xChemical4000000 0xD5000000 0xCFFFFF00. Reference Design Illustration Illustration APB register peripheral Desk 4-4 displays the mapping of the logic module signs up.

The addresses shown are usually offsets from the foundation addresses proven in Amount 4-2 on page 4-5. Offset deal with 0x0000000 0x0000004 0x0000008 0x000000C 0x0000010 0x0000014 Title Kind. 4.2.1 Oscillator divisor registers The oscillator signs up control the regularity of the clocks produced by the two clock generation devices on the logic component. Before creating to the oscillator registers, you must unlock them by creating the value 0x0000A05F by creating any worth various other than The referrals divider (R6:0) and VCO divider panel (V8:0) are utilized to determine the result rate of recurrence as follows: Regularity = 48MHz. Research Design Example You must also see the operating variety limitations: 10MHz.